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Inlet and outlet boundary conditions (BCs) play an important role in newly emerged image-based computational hemodynamics for blood flows in human arteries anatomically extracted from medical images. We developed physiological inlet and outlet BCs based on patients’ medical data and integrated them into the volumetric lattice Boltzmann method. The inlet BC is a pulsatile paraboloidal velocity profile, which fits the real arterial shape, constructed from the Doppler velocity waveform. The BC of each outlet is a pulsatile pressure calculated from the three-element Windkessel model, in which three physiological parameters are tuned by the corresponding Doppler velocity waveform. Both velocity and pressure BCs are introduced into the lattice Boltzmann equations through Guo’s non-equilibrium extrapolation scheme. Meanwhile, we performed uncertainty quantification for the impact of uncertainties on the computation results. An application study was conducted for six human aortorenal arterial systems. The computed pressure waveforms have good agreement with the medical measurement data. A systematic uncertainty quantification analysis demonstrates the reliability of the computed pressure with associated uncertainties in the Windkessel model. With the developed physiological BCs, the image-based computation hemodynamics is expected to provide a computation potential for the noninvasive evaluation of hemodynamic abnormalities in diseased human vessels. 

Secure Function Evaluation (SFE) has received recent attention due to the massive collection and mining of personal data, but remains impractical due to its large computational cost. Garbled Circuits (GC) is a protocol for implementing SFE which can evaluate any function that can be expressed as a Boolean circuit and obtain the result while keeping each party’s input private. Recent advances have led to a surge of garbled circuit implementations in software for a variety of different tasks. However, these implementations are inefficient, and therefore GC is not widely used, especially for large problems. This research investigates, implements, and evaluates secure computation generation using a heterogeneous computing platform featuring FPGAs. We have designed and implemented SIFO: secure computational infrastructure using FPGA overlays. Unlike traditional FPGA design, a coarse-grained overlay architecture is adopted which supports mapping SFE problems that are too large to map to a single FPGA. Host tools provided include SFE problem generator, parser, and automatic host code generation. Our design allows repurposing an FPGA to evaluate different SFE tasks without the need for reprogramming and fully explores the parallelism for any GC problem. Our system demonstrates an order of magnitude speedup compared with an existing software platform.